OptEM Inspector

OptEM Inspector is a device, interconnect and substrate extraction software tool for submicron digital, analog, and mixed-signal IC designs.

Product Description

Submicron IC designers face new challenges as feature sizes shrink, wires are more densely packed, and operating speeds increase. In this design environment interconnect delays play a dominant role, and second-order effects such as cross-coupling become significant. An electromagnetic analysis is required in today's complex high-performance designs in order to calculate accurate interconnect and device parasitics. OptEM Inspector is an interconnect and device extraction software tool for submicron digital, analog and mixed signal IC designs.

Interconnects, Devices and Substrate

OptEM Inspector is a software tool that screens the physical IC layout, and extracts the resistance and capacitance of the interconnects and devices. What is unique about OptEM Inspector is its capability to extract device substrate resistance in addition to the interconnect resistance and fringe, area, and lateral capacitances. The substrate resistance and lateral capacitance are critical because of their effect on crosstalk at the submicron level. Both 2D and 3D electromagnetic field analysis techniques are used to accurately and efficiently extract these RC values from the layout.

Physical Process Specification

The technology information required by OptEM Inspector is characterized through device mask combinations and a fabrication sequence. Initially, interconnects are described using a set of process steps where layers of dielectric and conductive materials are stacked upon one another at varying thicknesses and heights. No limitation is imposed on the number of metal layers. The 2D and 3D electromagnetic analysis supports conformal geometries and parametric variations of thickness, height, and conductor edges thereby providing a much greater degree of accuracy. Devices are described by identifying different combinations of mask layers.

Screening and Extraction

OptEM Inspector's screening and extraction depend on technology and layout information provided by the designer. This includes a fabrication process description, active device definition, and GDSII data. Inspector runs a 2D and 3D field solution to determine the interconnect and device parasitic RCs. The choice of field solution depends on the level of accuracy required. On output, OptEM Inspector provides a screening report listing the cell hierarchy, and circuit models of the extracted cells in standard output formats including SPICE, HSPICE, VHDL and others.

Features & Benefits

Features

layout extraction includes multi-terminal devices, cross overs, edge and mutual capacitances, and contact resistances
library of high-level devices and sub-cell models
technology independent with user-defined element definitions
analyzes the entire design or specific cells of the design
operates in a hierarchical, flat or mixed mode
handles non-orthogonal layouts with 45 degree angles
uses finite element resistance extraction and automated electromagnetic field solvers for greater accuracy
generates a standard SPICE net list and other formats
run time is linear to the size of the layout
economical use of computer memory
batch mode processing

Benefits

permits accurate simulation and modeling of the effect of interconnects on circuit performance
capable of handling digital, analog, or mixed designs using CMOS and/or bipolar technology
determines critical nets and characterizes cells when migrating from one process to another
provides flexibility in memory/disk requirements versus accuracy/calculation time
quickly determines problem nets based on criteria that are considered crucial to the performance of the design
provides detailed simulation in SPICE to determine time delays and signal integrity effects
fast run times
handles large layout files
allows for hands-off operation where calculations can proceed even when not logged in